IBM unveils 0.7 nm nanostack chip with 100B transistors

IBM presented a research prototype at VLSI 2026 from its Albany, New York, research center: a 0.7 nanometer node chip that places nearly 100 billion transistors on a fingernail-sized piece of silicon using a three-dimensional “nanostack” architecture.

The nanostack arranges transistors in two bonded vertical layers separated by an ultra-thin dielectric. By stacking and staggering devices, the design adds density in the vertical dimension rather than relying solely on smaller lateral features. IBM reported the transistor channel layers in the design are about 5 nanometers thick, roughly 15 silicon atoms, and said the 0.7 nm label reflects the generation of density and performance rather than literal feature sizes.

IBM compared the prototype to its 2021 2 nm work and reported nearly twice the transistor density, up to 50% higher performance in the test circuits presented, and up to 70% better energy efficiency. The company also reported roughly 40% improvement in SRAM scaling. IBM demonstrated functional CMOS inverter operation and provided switching performance data for the prototype.

The company described the result as a research demonstration rather than a commercial product. IBM outlined a path to production in about five years, pointing to 2031 as a possible timeframe for early adoption, and said the architecture could support further scaling for at least a decade beyond initial production. IBM noted additional development, manufacturing validation and supply-chain coordination remain before commercial chips can reach the market.

The Albany effort includes partners such as Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions. IBM plans to install a High Numerical Aperture extreme ultraviolet lithography tool from ASML at the Albany facility to support the next phases of logic scaling. Separately, the company announced plans to create Anderon, a standalone quantum foundry to manufacture quantum wafers at commercial scale.

Industry participants including large foundries and chipmakers are pursuing three-dimensional transistor approaches as two-dimensional feature shrinking faces limits such as quantum tunneling, heat dissipation and rising manufacturing cost. IBM framed the nanostack as a verified research path to sub-1 nm density through sequential vertical integration.

Jay Gambetta, director of IBM Research and an IBM Fellow, described the approach as a reinvention of chip construction intended to increase power and energy efficiency. Dan Hutcheson of Techinsights estimated the work could add another 10 to 15 years to the industry roadmap for logic scaling.